A bus bridge is used to interface different types of computer buses. For example, in a conventional computer, CPUs and system memory may be coupled to one another via a high-speed system bus. Input output ("I/O") devices, on the other hand, may be coupled to a slower-speed I/O bus. In such an architecture, the system bus and the I/O bus are typically interfaced by means of a bus bridge. The function of such a bus bridge generally is to handle the translation of speeds and protocols in such a manner that bus cycles may occur on either side of the bridge in relatively independent fashion.
A first-in-first-out or "FIFO" buffer is a well-known memory tool often used to transfer data from a source system to a destination system wherein the rate of output from the source system is not always the same as the rate of input of the destination system.
One of the challenges presented in the design of bus bridges is to provide adequate FIFO buffering to accommodate the speed differences between a system bus and I/O buses without unduly increasing system cost and complexity. For example, assume an architecture in which programmed I/O cycles ("PIO cycles") originating from a CPU on a system bus may be destined for any one of n different I/O buses depending on the addresses involved in each cycle. One method of handling such an architecture in the bus bridge design is to provide n separate conventional FIFO buffers, one for each of the n destination I/O buses. Each PIO cycle originating on the system bus may then be placed in the FIFO buffer that corresponds to that cycle's destination I/O bus.
Assume further that flow control on the system bus is indirect in the sense that, once the bus bridge indicates an I/O halt condition, numerous forthcoming PIO cycles may yet need to be processed by the bus bridge before all PIO cycles cease to issue from the system bus. In such a circumstance, the bus bridge cannot know in advance to which I/O buses these post-halt PIO cycles will be destined. A designer must therefore assume the worst-case scenario--that all of the post-halt PIO cycles will be destined for the I/O bus having the fullest FIFO buffer at the time the I/O halt indication is given.
The result of this assumption is deleterious in at least two ways: First, it means that, as a rule, an I/O halt indication must be issued by the bus bridge whenever any one of its n FIFO buffers reaches a state in which the buffer would be completely filled should all post-halt PIO cycles be destined for it. Such a rule would be unfortunate from a bandwidth efficiency standpoint if the worst-case scenario occurs only rarely. Second, it means that the aggregate FIFO storage capacity in the bus bridge will be wasted because no more than one of the FIFO buffers could ever become completely full in a system that operates under such a rule.
It is therefore an object of the present invention to provide a one-to-many bus bridge design in which FIFO storage capacity is used in a manner that improves bandwidth efficiency and reduces circuit size and cost.